intelligent frequency synthesizers preliminary data sheet pnp-1182-p22 features: ? 4160-4380 mhz frequency range ? programmable step size ? low integrated phase noise ? simplified programming applications: ? wireless infrastructure ? test equipment ? wireless lan description: the pnp-1182-p22 is a complete low noise frequency syn- thesizer, comprised of vco, pll, loop filter and data inter- face. the pnp family of rf signal sources is the world?s first truly configurable frequency synthesizer module. pnp technology offers the designer the ability to configure all of the synthesizer?s vital functions ?on the fly? with simple strings of code that contain the commands of start, stop, step, channel and ref. when new data is re- ceived, the pnp module optimizes its internal settings for best overall integrated phas e noise, switching speed and spurious suppression, all automatically and in less than 100 s. therefore, if the syst em requires 100 khz steps in mode #1 and 1 mhz step size in mode #2, these smart syn- thesizers can make quick adjustments with amazing accu- racy, speed and performance. control of the internal registers is accomplished through a serial data interface. many industry standard protocols are supported, including i 2 c, spi, and microwire serial in- terfaces. the pnp-1182-p22 is powered from +3v and +12.5v supplies delivering +3 dbm of rf output power. universal microwave corporation, 2339 destiny way, odessa, fl 33556 umc worldwide customer support center: 4703 s. lakeshore drive, suite 2, tempe, az 85282 1.877.umc.xtreme / fax 480.756.6026 package drawing all dimensions in inches microwire is a trademark of national semiconductor corp. spi is a trademark of motorola, inc. i 2 c is a trademark of philips corp. da1 ld da0 da2 n/c gnd gnd gnd gnd gnd gnd ref v1 gnd v2 rf top side bottom gnd gnd gnd gnd gnd gnd 0.100 0.180 0.260 0.340 0.420 0.500 0.100 0.180 0.260 0.340 0.500 0.380 0.220 0.460 0.300 0.140 0.380 0.220 0.460 0.300 0.140 0.000 0.600 0.000 0.000 0.600 0.600 0.600 0.000 0.420 0.000 0.220 pnp-1182-p22 4160-4380 mhz 4205 umc
pnp-1182-p22 specifications v1 = +12.5v, v2 = +3.0v, ref =20.0 mhz, -40 to +85c parameter min typ max units rf out characteristics frequency range 4160 4380 mhz output power 0 +3 +6 dbm harmonics -15 -10 dbc noise characteristics 1 khz offset ? noise -90 -85 dbc/hz 10 khz offset ? noise -93 -88 dbc/hz 100 khz offset ? noise -113 -108 dbc/hz 1 mhz offset ? noise -133 -128 dbc/hz spurious signals step = 2500 khz -70 -60 1 dbc dbc dbc ref feed-through -80 -70 dbc ref in characteristics ref input frequency 10 20 250 mhz ref input sensitivity 2 -5 0 +5 dbm ref input current +/-100 a logic inputs v inh , input high voltage 1.35 vdc v inl , input low voltage 0.6 vdc i inh , i inl , input current +/- 1 a c in , input capacitance 10 pf logic outputs v oh , output high voltage v 2 - 0.4 vdc v ol , output low voltage 0.4 vdc i oh , i ol , output current 500 a power supplies supply voltage, v 1 12.3 12.5 12.7 vdc supply voltage, v 2 2.7 3.0 3.3 vdc supply current, i 1 50 60 ma supply current, i 2 25 35 ma notes: 1. max step spurious are degraded by an additiona l 10 db at integer multiples of the reference frequency within a +/-100 khz bandwidth 2. ac coupled. for dc coupled, 0 - v 2 max.
pin descriptions pnp-1182-p22 mnemonic function rf rf output. this pin is ac coupled and should be connected to a non-reflective 50 ohm load. v1 supply input. decoupling capacitors to the ground plane should be placed as close as possi- ble to this pin. use an ultra low-noise regul ator followed by an rc filter for best noise. v2 supply input. decoupling capacitors to the ground plane should be placed as close as possi- ble to this pin. use an ultra low-noise regul ator followed by an rc filter for best noise. ref reference input. this is a cmos input with a nominal threshold of v 2 /2 and a dc equivalent input resistance of 100k ohms. this input can be driven from a cmos or ttl crystal clock oscillator or it can be ac coupled. gnd analog and rf ground. da0 serial interface. this input functions as cs in microwire/spi bus mo de. this input func- tions as sda in i 2 c bus mode. da1 serial interface. this input functions as data in microwire/spi bus mode. this input functions as scl in i 2 c bus mode. da2 serial interface. this input functions as clock in microwire/spi bus mode. this input must be connected to the digital ground in i 2 c bus mode. ld lock detect. this output is active high and provides a continuous digital lock status. absolute maximum ratings v 1 to ground -0.3 to +12.7 vdc v 2 to ground -0.3 to +3.6 vdc ref in to ground -0.3 to (v 2 + 0.3) vdc rf out to ground +/- 25 vdc digital i/o to ground -0.3 to (v 2 + 0.3) vdc operating temperature -40 to +85 c storage temperature -55 to +100 c stress above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only. operation of the dev ice above the conditions listed in the operational sections of this specification is not implied. ordering guide pnp-1182-p22 model i 2 c address type code pnp-1182-p22 default p003 pnp-1182a-p22 default + 1 p003 PNP-1182B-P22 default + 2 p003 pnp-1182c-p22 default + 3 p003 caution! esd (electrostatic discharge) sensitive dev ice. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can dis- charge without detection. although the pn p family of synthesizers feature esd protection circuitry, permanent damage ma y occur on devices subjected to high- energy electrostatic dischar ges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality
digital interface pnp-1182-p22 overview the pnp family of intelligent frequency synthesizers can be controlled through the use of a microprocessor inter- face or bus. several protocols are supported by pnp devices, although this specification will focus on spi bus, microwire-interface and i 2 c bus implementations. for spi and microwire applications, pnp devices re- quire a single 32 bit string of serial data to set frequency or to change its internal settings (figure 1). i 2 c bus util- izes some unique control bits and requires the addition of an address byte, increasing the serial bit-stream for this protocol to 40 bits per command (figure 2). the pnp device is programmed at the factory with pre- sets for the start, stop, step and reference registers. it is not necessar y to re-load any of these reg- isters if the factory values are acceptable. if the applica- tion requires different values than the factory pre-sets, then the pnp device must first be initialized by loading data into each of the affected registers. it is not neces- sary to re-load any registers that are already set properly for the application. start defines the lowest desired frequency of operation. stop defines the highest de- sired frequency of operation. step is used to channelize the band and reference defi nes the frequency of the external reference. once the pnp device is initialized, a fixed number channels are ava ilable. loading the chan- nel register sets the oper ating frequency of the pnp device. the formula for calculating the operating fre- quency is: start(hz) + (channel * step(hz)) = frequency(hz) microwire interface and spi bus microwire-interface and spi bus are extremely similar protocols (figures 6 & 7). data bits are clocked into the pnp device on the rising edge of the clock input. cs, or chip select not, must be in a low state for the in- coming data bits to be accepted. after all 32 bits have been clocked in, the cs line must transition high for the data string to be latched. after the string is latched, the information in the function block (figure 5) deter- mines where the data will be routed internally. i 2 c bus the i 2 c bus is a high-speed method of communicating over a two wire interface. pnp modules are configured as ?slaves? or receive-only devices and can only listen for commands from the ?master? which is typically a micro- processor. the i 2 c two wire bus consists of sda (serial data) and scl (serial clock) lines. in order to use the i 2 c bus for control of the pnp synthesizer module, the da2 line (see package drawing, page 1) must be tied to digi- tal ground. additionally, the sda and scl lines must be pulled up to d vdd using external resistors. multiple pnp devices can reside on the same two wire bus without the danger of corrupted data or data colli- sions. device selection is accomplished by sending a slave address preceding each string of data. if only one pnp device will be used on the i 2 c bus, then the factory pre-set base address will operate properly. if more than one pnp device will reside on the same i 2 c bus, then modules with unique address locations must be used. this should be specified when ordering (see ordering guide on page 3). for additional information refer to the i 2 c bus specification (c opyright philips corp). i 2 c implementation transferring data to pnp synthesizers using i 2 c protocol varies significantly from that of spi or microwire. pnp modules operate as slaves on the i 2 c bus and do not write to the bus. however, due to the fact that many devices might reside on the same bus, addressing must be used to direct the flow of data traffic. so, within the bit stream sent to the pnp device, there is a block of data that comprises the address by te. within this address byte there are 7 bits that are used for the address loca- tion and the eighth is used as a read/write (r/w) bit. since pnps are slaves and will never write to the i 2 c bus, this bit will always be set to 0 (logic low). each data string is sent using a series of five single byte blocks. i 2 c protocol requires that each string of data be- gin with a master generated start (s). each byte within the string must end with a slave generated ac- knowledge (a). finally, after all five bytes are gener- ated, the transfer is concluded with a master generated stop (p). the master generated stop must be exe- cuted following each data string for the values to be ac- cepted by the pnp device. if this condition is not satis- fied and a new master generated start occurs, the pnp device will purge the previous data without updating the desired attribute. repeated start (s r ) operation is not allowed when sending data to the pnp device. the flow of data bytes to the pnp device is outlined in figure 2. since function select and multiplier are 4 bits each, these blocks of data are combined into one byte. additionally, since the frequency/ channel block of data is 24 bi ts long, it must be frag- mented into three individual bytes as shown.
attribute definitions pnp-1182-p22 figure 4: function select (db28 - db31). after the data in frequency/channel (db0 - db23) is multiplied by 10 n where the value of n is determined by the contents of multiplier (figure 3), it is then routed internally to the start, stop, step, ref or channel registers based on the contents of func- tion select as shown below. db31 db30 db29 db28 function select fs3 fs2 fs1 fs0 0 0 0 0 channel. routes data from db0-db23 to the channel register. 0 0 0 1 start. routes data from db0-db23 to the start register. 0 0 1 0 stop. routes data from db0-db23 to the stop register. 0 0 1 1 step. routes data from db0-db23 to the step register. 0 1 0 0 reference. routes data from db0-db23 to the reference register all function select values not shown above are reserved for factory use. dbn db3 db2 db1 db0 frequency/channel fcn fc3 fc2 fc1 fc0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 1 1 1 1 15 db23 fc23 0 0 0 0 0 figure 2: frequency/channel (db0 - db23) this is a 24 bit string used to set the synthesizer?s start frequency, stop frequency, step frequency, ref frequency or channel number. figure 3: multiplier (db24 - db27) the data in frequency/channel (db0-db23) is multiplied by 10 n where the value of n is determined by the contents of multiplier (db24-db27) as shown below. db27 db26 db25 db24 multiplier m3 m2 m1 m0 0 0 0 0 10 0 x contents of db0-db23 0 0 0 1 10 1 x contents of db0-db23 0 0 1 0 10 2 x contents of db0-db23 0 0 1 1 10 3 x contents of db0-db23 n n n n 10 n x contents of db0-db23
figure 2: i 2 c bus data structure start slave address function select/multiplier s a6 a5 a4 a3 a2 a1 a0 r/w fs3 fs2 fs1 fs0 m3 m2 m1 m0 a 1 1 n n n n n 0 n n n n n n n n a pnp address (see table below) read/write acknowledge function select master start multiplier acknowledge acknowledge frequency/channel byte master stop frequency/channel stop fc 23 fc 22 fc 21 fc 20 fc 19 fc 18 fc 17 fc 16 a fc 15 fc 14 fc 13 fc 12 fc 11 fc 10 fc 9 fc 8 fc 7 fc 6 fc 5 fc 4 fc 3 fc 2 fc 1 fc 0 a p n n n n n n n n n n n n n n n n n n n n n n n n n a acknowledge frequency/channel byte acknowledge frequency/channel byte i 2 c address a6 a5 a4 a3 a2 a1 a0 pnp-1182-p22 1 1 0 0 0 0 0 pnp-1182a-p22 1 1 0 0 0 0 1 PNP-1182B-P22 1 1 0 0 0 1 0 pnp-1182c-p22 1 1 0 0 0 1 1 pnp-1182x-p22 1 1 n n n n n model number function select (4 bits) multiplier (4 bits) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db n db2 db1 db0 fs3 fs2 fs1 fs0 m3 m2 m1 m0 fc23 fc22 fc n fc2 fc1 fc0 frequency/channel (24 bits) data structures pnp-1182-p22 figure 1: spi bus/microwire-interface data structure
spi bus/microwire-interface timing characteristics figure 6: microwire interface timing diagram db31 db30 db1 db0 db2 ~ ~ ~ ~ clock data cs t 1 t 2 t 3 t 4 t 6 t 5 parameter limit at t min to t max units test conditions/comments t 1 100 ns min data to clock setup time t 2 100 ns min data to clock hold time t 3 250 ns min clock high time t 4 250 ns min clock low time t 5 100 ns min clock to cs setup time t 6 200 ns min cs pulse width (applies to microwire interface only) t 7 200 ns min cs to clock setup time (applies to spi bus only) figure 7: spi bus timing diagram db31 db30 db1 db0 db2 ~ ~ ~ ~ clock data cs t 1 t 2 t 3 t 4 t 5 t 7
a 0.043 0.046 0.049 b 0.052 0.055 0.058 c 0.475 0.480 0.485 d 0.535 0.540 0.545 e 0.080 recommended layout dimensions (min) (typ) (max) package drawing all dimensions in inches recommended layout all dimensions in inches tape and reel specifications all dimensions in mm bo 15.5 f 10.2 p 16.0 c 0.06 po 4.0 d 0.30 cw 24.0 tw 21.2 d 1.5 ko 6.6 tape and reel dimensions ao 15.5 e 1.75 c c a a b b d e da1 ld da0 da2 n/c gnd gnd gnd gnd gnd gnd ref v1 gnd v2 rf top side bottom gnd gnd gnd gnd gnd gnd 0.000 0.220 pnp-1182-p22 4160-4380 mhz 4205 umc 0.100 0.180 0.260 0.340 0.420 0.500 0.100 0.180 0.260 0.340 0.500 0.380 0.220 0.460 0.300 0.140 0.380 0.220 0.460 0.300 0.140 0.000 0.600 0.000 0.000 0.600 0.600 0.600 0.000 0.420
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